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? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 fan6520a single synchr onous buck pwm controller october 2006 fan6520a single synchronous buck pwm controller features output range: 0.8v to v in ? 0.8v internal reference ? 1.5% over line voltage and temperature drives n-channel mosfets simple single-loop control design ? voltage-mode pwm control fast transient response ? high-bandwidth error amplifier ? full 0% to 100% duty cycle lossless, programmable, over-current protection ? uses upper mosfet?s r ds(on) small converter size ? 300khz fixed-frequency oscillator ? internal soft-start ? 8-lead soic applications power supplies for pc subsystems and peripherals mch, gtl, and agp supplies cable modems, set-top boxes, and dsl modems dsp, memory low-voltage distributed power supplies description the fan6520a simplifies implementing a complete con- trol and protection scheme for a dc-dc stepdown con- verter. designed to drive n-channel mosfets in a synchro-nous buck topology, the fan6520a integrates the control, output adjustm ent, monitoring, and protec- tion functions into a single 8-lead package. the fan6520a employs a single feedback loop and volt- age-mode control with fast transient response. the out- put voltage can be precisely regulated to as low as 0.8v, with a maximum tolerance of 1.5% over-temperature and line-voltage variations. a fixed-frequency oscillator reduces design complexity, while balancing typical appli- cation cost. the error amplifier features a 15mhz gain- bandwidth product and an 8v/s slew rate, which enables high converter bandwidth for fast transient per- formance. the resulting pwm duty cycles range from 0% to 100%. the ic monitors the drop across the upper mosfet and inhibits pwm operation appropriately to protect against over-current conditions. this approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. the fan6520a is rated for operation from 0 to +70c, with the fan6520ai rated from ?40 to +85c. ordering information part number temperature range package packing fan6520am 0c to 70c soic-8 rails fan6520amx 0c to 70c soic-8 tape and reel fan6520aim ?40c to 85c soic-8 rails fan6520aimx ?40c to 85c soic-8 tape and reel
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 2 fan6520a single synchr onous buck pwm controller pin configuration fan6520am 8-pin soic package pin definitions pin # name description 1 boot bootstrap supply input. provides a boosted voltage to the high-side mosfet driver. connect to bootstrap capacitor, as shown in figure 1. 2 hdrv high-side gate-drive output. connect to the gate of the high-side power mosfet(s). this pin is monitored by the adaptive shoot-th rough protection circuitry to determine when the upper mosfet has turned off. 3gnd ground. the signal and power ground for the ic. tie this pin to the ground island/plane through the lowest impedance connection availabl e. connect directly to source of low-side mosfet(s). 4ldrv low-side gate-drive output. connect to the gate of the low-side power mosfet(s). this pin is monitored by the adaptive shoot-th rough protection circuitry to determine when the lower mosfet has turned off. 5vcc vcc. provides bias power to the ic and the drive voltage for ldrv. bypass with a ceramic capacitor as close to this pin as possible. 6fb feedback. this pin is the inverting input of the internal error amplifier. use this pin, in com- bination with the comp/ocset pin, to comp ensate the voltage-control feedback loop of the converter. 7comp/ ocset/sd compensation / over-current set point / shut down. this is a multiplexed pin. during operation, the output of the error amplifier drives this pin. during a short period of time fol- lowing power-on reset (por), this pin is used to determine the over-current threshold of the converter. pulling comp/ocset to a level below 0.8v disables the c ontroller. disabling the controller causes the oscillator to stop, the hdr v and ldrv outputs to be held low, and the soft-start circuitry to restart. 8sw switch node input. the sw pin provides return for the high-side bootstrapped driver, is a sense point for the adaptive s hoot-through protection, and is used to monitor the drop across the upper mosfet?s r ds(on) for current limit. connect as shown in figure 1. fan6520a 1 2 3 4 8 7 6 5 sw comp/ocset/sd fb vcc boot hdrv gnd ldrv
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 3 fan6520a single synchr onous buck pwm controller typical application figure 1. typical application figure 2. functional block diagram fb fan6520a vcc +v out q2 comp/ocset r s gnd ldrv sw hdrv boot 5 3 4 8 2 1 6 7 q1 c hf r offset r ocset c f r f c i c boot d boot c bulk c vcc +5v l out c out inhibit pwm 0.8v error amp vcc osc gate control logic fb pwm por / soft-start v cc comp/ocset g nd gnd ldrv sw hdrv boot sample & hold 20a oc
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 4 fan6520a single synchr onous buck pwm controller absolute maximum ratings the ?absolute maximum ratings? are those values beyond wh ich the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. th e ?recommended operating conditions? table defines the conditions for actual device operation. thermal information recommended oper ating conditions parameter min. max. units vcc to gnd 6v vboot to gnd 15 v hdrv (v boot ? v sw )6v ldrv ?0.5 6 v sw to pgnd continuous ?0.5 6 v transient ( t < 50ns, f < 500khz) ?3 7 v all other pins 5.5 v symbol parameter min. typ. max. units t stg storage temperature ?65 150 c t l lead soldering temperature, 10 seconds 300 c vapor phase, 60 seconds 215 c infrared, 15 seconds 220 c p d power dissipation, t a = 25c 715 mw jc thermal resistance, junction-to-case 40 c/w ja thermal resistance, junction-to-ambient 140 c/w symbol parameter conditions min. typ. max. units v cc supply voltage vcc to pgnd 4.5 5 5.5 v t a ambient temperature fan6520a 0 70 c fan6520ai ?40 85 c t j junction temperature ?40 125 c
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 5 fan6520a single synchr onous buck pwm controller electrical specifications v cc = 5v and t a = 25c, using the circuit shown in figure 1 unless ot herwise noted. the ? denot es specifications that apply over the full oper ating temperature range. notes: 1. all limits at operating temperature ex tremes are guaranteed by design, char acterization, and statistical quality control. 2. ac specifications guaranteed by design/ characterization (not production tested). symbol parameter conditions min. typ. max. units supply current i vcc v cc current hdrv, ldrv open ? 1.5 2.4 3.8 ma power-on reset por rising vcc por thre shold ? 4.00 4.22 4.45 v vcc por threshold hysteresis 170 mv oscillator f osc frequency fan6520a ? 250 300 340 khz fan6520ai ? 230 300 340 khz v osc ramp amplitude ? 1.5 vp-p reference v ref reference voltage t a = 0 to 70c ? 788 800 812 mv fan6520ai ? 780 800 820 mv error amplifier dc gain 88 db gbwp gain ? bandwidth product 15 mhz s/r slew rate 8 v/s gate drivers r hup hdrv pulll-up resistance 2.5 r hdn hdrv pull-down resistance 2.0 r lup ldrv pull-up resistance 2.5 r ldn ldrv pull-down resistance 1.0 protection/disable i ocset ocset current source fan6520a ? 17 20 22 a fan6520ai ?142024 a v disable disable threshold 800 mv
?2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 6 fan6520a single synchr onous buck pwm controller circuit description initialization the fan6520a automatically initializes upon receipt of power. the power-on reset (por) function continually monitors the bias voltage at the vcc pin. when the sup- ply voltage exceeds its por threshold, the ic initiates the over-current protection (ocp) sample-and-hold operation. upon completion of the ocp sample-and-hold operation, the por function initiates soft-start operation. over-current protection the over-current function protects the converter from a shorted output by using th e upper mosfet?s on-resis- tance, r ds(on) , to monitor the current. this method enhances the converter?s efficiency and reduces cost by eliminating the need for a current-sensing resistor. the over-current function cycles the soft-start function in a hiccup mode to provide fault protection. a resistor (r oc- set ) programs the over-current trip level (see typical application diagram). imme diately following por, the fan6520a initiates the over-current protection sam- pling-and-hold operation. firs t, the internal error ampli- fier is disabled. this allows an internal 20a current sink to develop a voltage across r ocset . the fan6520a then samples this voltage at the comp pin. this sam- pled voltage, which is referenced to the vcc pin, is held internally as the over-current set point. when the voltage across the upper mosfet, which is also referenced to the vcc pin, exceeds the ov er-current set point, the over-current function initiate s a soft-start sequence. fig- ure 3 shows the inductor current after a fault is intro- duced while running at 15a. the continuous fault causes the fan6520a to go into a hiccup mode with a typical period of 25ms. the inductor current increases to 18a during the soft-start interval and causes an over-current trip. the converter dissipates very little power with this method. the measured input power for the conditions shown in figure 3 is 1.5w. figure 3. over-current operation the over-current function trips at a peak inductor current (i peak ) determined by: where i ocset is the internal ocset current source (20a typical). the oc trip point varies mainly due to the mosfet?s r ds(on) variations. to avoid over-current tripping in the normal operating load range, find the r oc- set resistor from the equation above with: ? the maximum r ds(on) at the highest junction temperature ? the minimum i ocset from the specification table ? determine i peak for where i is the output inductor ripple current. for an equation for the ripple current, see ?output induc- tor (l out )? under component selection. internal circuitry of the fan6520a does not recognize a voltage drop across r ocset larger than 0.5v. any volt- age drop across r ocset greater than 0.5v sets the over- current trip point to: an over-current trip cycles the soft-start function. soft-start the por function initiates the soft-start sequence after the over-current set point has been sampled. soft-start clamps the error amplifier output (comp pin) and refer- ence input (noninverting terminal of the error amp) to the internally generated soft-start voltage. figure 4 shows a typical start-up interval where the comp/ocset pin has been released from a grounded (system shutdown) state. initially, the comp/ocset is used to sample the over-current set point by dis abling the error amplifier and drawing 20a through r ocset . once the over-current level has been sampled, the soft-start function is initi- ated. the clamp on the error amplifier (comp/ocset pin) initially controls the c onverter?s output voltage during soft-start. the oscillator?s triangular waveform is com- pared to the ramping error amplifier voltage. this gener- ates sw pulses of increasing width that charge the output capacitor(s). when the internally generated soft- start voltage exceeds the feedback (fb pin) voltage, the output voltage is in regulation. this method provides a rapid and controlled output voltage rise. the entire start- up sequence typically takes about 11ms. output inductor current 5a/div. i peak i ocset r ocset r ds on () ----------------------------------------------- = (1) i peak i out max () i 2 ----- + > i peak 0.5v r ds on () ---------------------- = (2)
?2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 7 fan6520a single synchr onous buck pwm controller figure 4. soft-start interval the fan6520a incorporates a mosfet shoot-through protection method that allows a converter to both sink and source current. care should be exercised when designing a converter with the fan6520a when it is known that the converter may sink current. when the converter is sinking current, it is behaving as a boost converter regulating its input voltage. this means that the converter is boosting current into the v cc rail, which supplies the bias voltage to the fan6520a. if this current has nowhere to go?such as to other distributed loads on the v cc rail, through a voltage limiting protec- tion device, or other meth ods?the capacitance on the v cc bus absorbs the current. this allows the voltage level of the v cc rail to increase. if the voltage level of the rail is boosted to a level t hat exceeds the maximum volt- age rating of the fan6520a, the ic experiences an irre- versible failure and the converter is no longer operational. ensure that there is a path for the current to follow, other than the capaci tance on the rail, to prevent this failure mode. application information layout considerations in any high-frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. use wide, short-printed traces to minimize inter- connecting impedances. the critical components should be located as close together as possible, using ground plane construction or single-point grounding. figure 5. printed circuit board power and ground planes or islands figure 5 shows the critical power components of the con- verter. to minimize voltage overshoot, the interconnect- ing wires (indicated by heavy lines) should be part of a ground or power plane in a printed circuit board. the components shown in figure 5 should be located as close together as possible. note that the capacitors c in and c out may each represent numerous physical capac- itors. locate the fan6520a within two inches of the q1 and q2 mosfets. the circuit traces for the mosfets? gate and source connections from the fan6520a must be sized to handle up to 1a peak current. figure 5 shows the circuit traces that require additional layout consideration. use single point and ground plane construction for the circuits shown. minimize any leakage current paths on the comp/ocset pin and locate the resistor, r oscet, close to the comp/ocset pin because the internal current source is only 20a. pro- vide local v cc decoupling between the vcc and gnd pins. locate the capacitor, cboot, as close as practical to the boot and phase pins. all components used for feedback compensation should be located as close to the ic as practical. figure 6. pcb small signal layout guidelines +v out q2 ldrv sw hdrv q1 c in l out c out load vin +v out q2 vcc sw boot l out c out load gnd c boot c vcc +5v d boot fan6520a q1 vin comp/ocset r ocset +5v
?2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 8 fan6520a single synchr onous buck pwm controller feedback compensation figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier (error amp) output (v e/a ) is compared with the oscillator (osc) tri angular wave to provide a pulse-width modulated (pwm) wave with an amplitude of v in at the sw node. the pwm wave is smoothed by the output lc filter (l out and c out ). figure 7. voltage mode buck converter compensation design the modulator transfer functi on is the small-signal trans- fer function of v out /v comp . this function is dominated by a dc gain and t he output filter (l out and c out ), with a double-pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is the input voltage (v in ) divided by the peak-to-peak oscillator voltage ( v osc . ) the following equations define the modulator break fre- quencies as a function of the output lc filter: the compensation network consists of the error amplifier (internal to the fan6520a) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed-loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase mar- gin. phase margin is the difference between the closed- loop phase at f 0db and 180 degrees. the equations below relate the compensation network?s poles, zeros, and gain to the components (r1, r2, r3, c1, c2, and c3), shown in figure 7. use the following steps to locate the poles and zeros of the compensation network: 1. pick gain (r2/r1) for the desired converter band- width. 2. place the first zero below the filter?s double pole (~75% f lc ). 3. place the second zero at filter?s double pole. 4. place the first pole at the esr zero. 5. place the second pole at half the switching fre- quency. 6. check the gain against the error amplifier?s open- loop gain. 7. estimate phase margin. repeat if necessary. figure 8 shows an asymptotic plot of the dc-dc con- verter?s gain vs. frequency. the actual modulator gain has a high gain peak due to the high q factor of the out- put filter and is not shown in figure 8. using the above guidelines should give a compensation gain similar to the curve plotted. the open-loop error amplifier gain bounds the compensation gain. check the compensation gain at fp2 with the capabilities of the error amplifier. the closed-loop gain is constructed on the graph of fig- ure 8 by adding the modulator gain (in db) to the com- pensation gain (in db). this is equivalent to multiplying the modulator tran sfer function by the compensation transfer function and plotting the gain. the compensation gain uses external impedance net- works z fb and z in to provide a stable high bandwidth overall loop. a stable control loop has a gain crossing with a ?20db/decade slope and a phase margin greater than 45. include worst-case component variations when determining phase margin. z fb comp fb +v out q2 l out c out +5v v in sw esr 0.8v error amp pwm osc detailed compensation components comp fb 0.8v error amp c1 r2 c3 r3 c2 r1 z in v out z fb z in f lc 1 2 lc ------------------------- = (3) f esr 1 2 esr c ------------------------------------ = (4) f z1 1 2 r 2 c 1 --------------------- - = (5) f p1 1 2 r 2 c 1 c 2 c 1 c 2 + -------------------- ?? ?? ---------------------------------------- - = (6) f z2 1 2 c 3 r 1 r 3 + () ---------------------------------------- = (7) f p2 1 2 r 3 c 3 --------------------- - = (8)
?2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 9 fan6520a single synchr onous buck pwm controller figure 8. asymptotic bode plot of converter gain an output capacitor is require d to filter the output and supply the load transient current. the filtering require- ments are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. thes e requirements are generally met with a mix of capacitors and careful layout. component selection output capacitors (c out ) modern components and loads are capable of producing transient load rates above 1a/ns. high-frequency capac- itors initially supply the transient and slow the current load rate seen by the bulk capacitors. effective series resistance (esr) and voltage rating are typically the prime considerations for the bulk filter capacitors, rather than actual capacitance requirements. high-frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the performanc e of these low-inductance components. consult with the load manufacturer on spe- cific decoupling requirements. use only specialized low- esr capacitors intended for switching-regulator applica- tions for the bulk capacitors . the bulk capacitor?s esr determines the output ripple voltage and the initial volt- age drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr available in larger case sizes; how- ever, the equivalent series inductance (esl) of these capacitors increases with ca se size and can reduce the usefulness of the capacitor to high slew-rate transient loading. since esl is not a specified parameter, work with the capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable compo- nent. generally, multiple smal l-case electrolytic capaci- tors perform better than a single large-case capacitor. output inductor (l out ) the output inductor is select ed to meet the output volt- age ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple volt- age ( v) and current ( i) are approximated by the fol- lowing equations: increasing the inductance value reduces the ripple cur- rent and voltage, but also reduces the converter?s ability to quickly respond to a load transient. one of the param- eters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control-loop design, the fan6520a provides either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transien t current level. during this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. depending on whether there is a load application or a load removal, the response time to a load transient (i step ) is different. the following equations give the approximate response time interval for application and removal of a transient load: where t rise is the response time to the application of a positive i step and t fall is the response time to a load removal (negative i step ). the worst-case response time can be either at application or removal of load. check both of these equations at the minimum and maximum output levels for the wo rst-case response time. input capacitor selection use a mix of input bypass capa citors to cont rol the volt- age overshoot across the mo sfets. use small ceramic capacitors for high-frequency decoupling and bulk capacitors to supply the current needed each time q1 turns on. place the small ce ramic capacitors physically close to the mosfets and between the drain of q1 and the source of q2. the important parameters for the bulk input capacitor are the voltage rating and the rms cur- rent rating. for reliable operat ion, select the bulk capaci- tor with voltage and current ratings above the maximum input voltage and the largest rms current required by the circuit. the capacitor voltage rating should be at least 100 80 60 40 20 0 -20 -40 -60 10 100 1k 10k 100k frequency (hz) open loop error amp gain compensation gain closed loop gain modulator gain 20log (v in /dv osc ) 20log (r 2 /r 1 ) f z1 f z2 f p1 f lc f esr f p2 gain (db) 1m 10m i v in v out ? f sw l ----------------------------- - ?? ?? ?? v out v in -------------- = vesr i (9) t rise li step v in v out ? ----------------------------- - = (10) t fall li step v out ------------------------ = (11)
?2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 10 fan6520a single synchr onous buck pwm controller 1.25 times greater than the maximum input voltage. a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement (i rms ) for the input capacitor of a buck regulator is: where the converter duty cycle is . for a through-hole design, several electrolytic capacitors may be needed. for surface-mount designs, solid tanta- lum capacitors can be used, but caution must be exer- cised with regard to the capacitor?s surge current rating. the capacitors must be capable of handling the surge current at power-up. some capacitor series available from reputable manufacturers are surge current tested. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ) and the internal diode, as shown in figure 1. select these components after the high-side mosfet has been chosen. the required capacitance is deter- mined using the following equation: where q g is the total gate charge of the high-side mos- fet and v boot is the voltage droop allowed on the high-side mosfet drive. to prevent loss of gate drive, the bootstrap capacitance should be at least 50 times greater than the c iss of q1. thermal considerations total device dissipation: p d = p q + p hdrv + p ldrv (14) where p q represents quiescent power dissipation. p q = v cc [4ma + 0.036 (f sw ? 100)] (15) where f sw is switching frequency (in khz). p hdrv represents internal power dissipation of the upper fet driver. p hdrv = p h(r) p h(f) (16) where p h(r) and p h(f) are internal dissipations for the rising and falling edges respectively. where: p q1 = q g1 v gs(q1) f sw (19) where q g1 is total gate charge of q1 for its applied v gs . as described in the equations above, the total power consumed in driving the gate is divided in proportion to the resistances in series with the mosfet's internal gate node, as shown in figure 9. figure 9. driver dissipation model r g is the polysilicon gate resistance internal to the fet. r e is the external gate dr ive resistor implemented in many designs. note that the introduction of r e can reduce driver power dissipation, but excess r e may cause errors in the ?adaptive gate drive? circuitry. for more information, please refer to application note an- 6003, ?shoot-through? in synchronous buck converters at http://www.fairchildsem i.com/an/an/an-6006.pdf. p ldrv is dissipation of the lower fet driver. p ldrv = p l(r) p l(f) (20) where p h(r) and p h(f) are internal dissipations for the rising and falling edges, respectively: where: p q2 = q g2 v gs(q2) f sw. (23) power mosfet selection for more informat ion on mosfet sele ction for synchro- nous buck regulators, refer to: an-6005: synchronous buck mosfet loss calculations at http://www.fairchild- semi.com/an/an/an-6005.pdf. losses in a mosfet are the sum of its switching (p sw ) and conduction (p cond ) losses. in typical applications, the fan6520a converter's output voltage is low with respect to its input voltage; therefore the lower mosfet (q2) is co nducting the full load cur- rent for most of the cycle. choose a mosfet for q2 that has low r ds(on) to minimize conduction losses. in contrast, the high-side mosfet (q1) has a much shorter duty cycle and its co nduction loss has less impact. q1, however, sees mo st of the sw itching losses, so q1?s primary selection cr iteria should be gate charge. i rms i l dd 2 ? () = (12) d v out v in -------------- = c boot q g v boot ------------------------- - = (13) p hr () p q1 r hup r hup r e r g ++ ------------------------------------------- - = (17) p hf () p q1 r hdn r hdn r e r g ++ ------------------------------------------- - = (18) hdrv q1 g r g r e r hup boot sw r hdn s p lr () p q2 r lup r lup r e r g ++ ------------------------------------------ - = (21) p lf () p q2 r ldn r hdn r e r g ++ ------------------------------------------- - = (22)
?2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 11 fan6520a single synchr onous buck pwm controller high-side losses figure 10 shows a mosfet?s switching interval, with the upper graph being the voltage and current on the drain- to-source and the lower graph detailing v gs vs. time with a constant current charging the gate. the x-axis, there- fore, is also representative of gate charge (q g ). c iss = c gd + c gs and it controls t1, t2, and t4 timing. c gd receives the current from the gate driver during t3 (as v ds is falling). the gate charge (q g ) parameters on the lower graph are either spec ified or can be derived from the mosfet?s datasheet. assuming switching losses ar e about the same for both the rising edge and falling edge, q1?s switching losses occur during the shaded time when the mosfet has voltage across it and current through it. these losses are given by: p upper = p sw + p cond (24) where p upper is the upper mosfet?s total losses, p sw and p cond are the switching and conduction losses for a given mosfet, r ds(on) is at the maximum junction tem- perature (t j ), and t s is the switching period (rise or fall time) and is t2+t3 (figure 10). the driver?s impedance and c iss determine t2, while t3?s period is controlled by the driver?s impedance and q gd . since most of t s occurs when v gs = v sp, use a constant current assumption for the driver to simplify the calcula- tion of t s : figure 10. switching losses and q g figure 11. drive equivalent circuit most mosfet vendors specify q gd and q gs . q g(sw) can be determined as q g(sw) = q gd + q gs ? q th where q th is the gate charge required to reach the mosfet threshold (v th ). for the high-side mosfet, v ds = v in , which can be as high as 20v in a typical portable appli- cation. care should be taken to include the delivery of the mosfet?s gate power (p gate ) in calculating the power dissipation required: p gate = q g v cc f sw (28) where q g is the total gate charge to reach v cc . p sw v ds i l 2 ----------------------- - 2 t s ?? ?? f sw = (25) p cond v out v in ----------------- ?? ?? ?? i out 2 r ds on () = (26) t s q gsw () i driver ------------------------- - q gsw () v cc v sp ? r driver r gate + --------------------------------------------------------- ?? ?? ?? -------------------------------------------------------------- - ? (27) v sp t1 t2 t3 4.5v t4 t5 q g(sw) v ds i d q gs q gd v th v gs c iss c gd c iss c gd r d r gate c gs hdrv 5v sw v in g
?2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 12 fan6520a single synchr onous buck pwm controller low-side losses q2, however, switches on or off with its parallel shottky diode conducting, therefore v ds y 0.5v. since p sw is proportional to v ds , q2?s switching losses are negligible and q2 can be selected based on r ds(on) only. conduction losses for q2 are given by: p cond = (1-d) i out 2 r ds(on) (29) where r ds(on) is the r ds(on) of the mosfet at the highest operating junction temperature and is the minimum duty cycle for the converter. since d min < 20% for portable computers, (1-d) 1 pro- duces a conservative result, simplifying the calculation. the maximum power dissipation (p d(max ) ) is a function of the maximum allowable die temperature of the low- side mosfet, the j-a , and the maximum allowable ambient temperature rise: depends primarily on the amount of pcb area that can be devoted to heat sinking. refer to fairchild application note an-1029 maximum power enhancement tech- niques for so-8 power mosfets at http://www.fairchild- semi.com/an/an/an-1029.pdf . d v out v in ----------------- = p dmax () t jmax () t amax () ? ja ? ---------------------------------------------------------- = (30)
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 13 fan6520a single synchr onous buck pwm controller typical application circuit figure 12. 5v to 1.5v 15a dc-dc converter evaluation board bill of materials (1.5v, 15 amps): ref des description manufacturer p/n qty c1 100pf capacitor, 603 any 1 c2 0.01f capacitor, 603 any 1 c3 not populated 0 c4 0.1f capacitor, 603 any 1 c5a,c5b 1f capacitor, 805 any 3 c6,c11 0.1f capacitor, 603 any 2 c7 not populated capacitor, 603 any 0 c9-10,c12,c13 1500f capacitor, 6.3v united chemi-con kzj6.3vb152m10x12ll 4 d1 diode, 30ma, 30v fairchild mmsd4148 1 l1 1.2h inductor intertechnical sc5015-1r2m 1 q1,q2 mosfet fairchild fdd6606 2 r1 2.2k 1% resistor, 603 any 1 r2 30.1k 1% resistor, 603 any 1 r3 not populated 0 r4 2.49k resistor, 603 any 1 r5 11.8k resistor, 603 any 1 r6 not populated resistor, 603 any 0 r7 0 resistor, 603 any 1 pb1 pushbutton, miniature digikey p8007s-nd 1 u1 single synchronous buck pwm fairchild fan6520a 1 tp1,2,3,4 test points keystone 1514-2 4 fb u1 fan6520a vcc +v out q2 comp/ocset r7 gnd ldrv sw hdrv boot 5 3 4 8 2 1 6 7 q1 c5a r4 r5 c2 r2 c1 c6 d1 c13 c4 +5v l out c9-10 sw1 c12 c5b c7 c3 r1 r3 c11 r6
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 14 fan6520a single synchr onous buck pwm controller dimensional outline drawing figure 13. 8-lead soic package drawing
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan6520a rev. 1.0.5 15 fan6520a single synchr onous buck pwm controller

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